C-Element Metastability Mitigation using Schmitt-Trigger

As all state holding elements, Muller C-elements are prone to metastable upsets [1], [2], [3]. In case of an input spike or a short overlap of both input signals, a metastable state may arise in the element. The cause for the problem is that the storage loop starts to flip its state but while doing so, the input is removed and the loop is left in an undecided state. Based only on the characteristics of the loop, the resolution process may take an arbitrary long time. The outcome of the resolving process can either be a flip of the state, or the state my not change after all. Figure 1 shows the typical behavior of a metastable logic gate. It can be seen that the storage loop starts to change its value but then enters the metastable region and does not leave it for an extended time. The resolution may be either of the both stable states. While the resolving process is active, the nodes of the storage loop are at intermediate, analog voltage levels [2]. The voltage levels as well as the metastable response may be estimated using a Spice analysis [4]. As has been previously shown [5], metastability is unavoidable. Therefore one can not hope to devise a functioning countermeasure eliminating metastability. It may nevertheless be possible to mitigate or convert the malicious effects of metastability into a more benign form. This conversion is even more essential as metastability may fool conventional error containment circuits (like voters, e.g.) [6]. Such a containment is especially important for asynchronous circuits. In contrast to synchronous circuits no temporal masking is present, meaning that the asynchronous circuit may propagate the erroneous state immediately, whereas the propagation in synchronous circuits is only done at clock edges. Therefore it is unacceptable to generate even Figure 2. Metastability mitigation principle